CVTTSS2SI--Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer with Truncation
sample: cvttss2si ebx,xmm0Opcode |
Instruction |
Description |
|---|---|---|
F3 0F 2C /r
|
CVTTSS2SI r32,
xmm/m32
|
Convert one single-precision floating-point
number from xmm/m32 to one signed
doubleword integer r32 using
truncation.
|
Description
Converts a single-precision floating-point value in the source operand (second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.When a conversion is inexact, a truncated result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
Operation
DEST[31-0]
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31-0]);
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31-0]);Intel(R) C++ Compiler Intrinsic Equivalent
int_mm_cvttss_si32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision.Protected Mode Exceptions
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
#AC - For unaligned memory reference if the current privilege level is 3.
Real-Address Mode Exceptions
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode.#PF(fault-code) - For a page fault.
#AC - For unaligned memory reference if the
current privilege level is 3.

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